1. Field of the Invention
The present invention relates to a digital FIFO (First-In First-Out) memory.
2. Description of the Prior Art
The memory is comprised of n parallel signal channels having their inputs connected to the data input of the memory and having their outputs coupled to the data output of the memory, each signal channel containing m series-connected, identical memory cells each having an enable input, and clock signals being applied to the memory cells in such a way that memory cells which are adjacent in the direction of signal flow are rendered conductive one after the other. Such a FIFO memory is described in U.S. Pat. No. 3,708,690, for example.
The prior art memory cell consists of a level regenerator followed by a transfer transistor. The level regenerator consists of two transistors having their controlled current paths connected in parallel between the clock input and the controlled current path of the transfer transistor. The other end of the current path of this transfer transistor is connected to the gate of one of the level-regenerator transistors of the next memory cell and, through a capacitor, to the reference point for the clock signal, while the gate of the other level-regenerator transistor is connected to the clock input, and the gate of the transfer transistor is the enable input.
This prior art FIFO memory, but also that disclosed in applicant's EP-A 243 528 (ITT case B. Giebel et al 8-2), which was not published prior to the filing date of the present application, are operated exclusively by clock signals derived from a single basic clock signal.
By contrast, the object of the invention as claimed is to improve the prior art FIFO memory and the FIFO memory of the prior referenced application in such as way that an input-data rate is so moved through the FIFO memory that the output-data stream appears at an output-data rate momentarily different from the input-data rate, the two data rates being equal on a time average, however, so that data can simultaneously be written into and read from the FIFO memory at different data rates.
The invention has a similar advantage as that offered by applicant's prior proposal over the prior art described in the U.S. patent referred to above, namely that the above-mentioned capacitor can be dispensed with, so that the amount of area required by the FIFO memory on an integrated-circuit chip is reduced.